Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) are commonly used to develop and implement complex digital designs. Such devices include a variety of configurable digital logic elements, including combinatorial and sequential logic elements. Combinatorial logic elements include, for example, programmable look-up tables and logic gates such as “AND” gates and “OR” gates, while sequential logic elements include memory elements such as “flip-flops” and “latches.”
Many programmable logic devices now include configurable logic blocks (CLBs) and pre-designed, hardwired logical structures or “cores.” CLBs are groups of logic elements that form the basic programmable element of the device. Each CLB typically includes a collection of combinatorial and sequential elements placed on the device and interconnected according to a pre-determined and uniform pattern. Pre-designed cores, also referred to as “firm-IP” cores or just “firm” cores, facilitate the development process by giving the programmable device pre-determined functionality. Examples of firm cores include digital processors and network interconnections.
Programmable logic devices are favored by many developers because they are easily configured and reconfigured, facilitating the development cycle of testing a design, making changes accordingly, and retesting. Design typically begins with “high level” development, wherein an engineer creates the design using a hardware description language, such as VHDL or Verilog, or a circuit schematic design entry tool. Design testing usually begins at the high level to ensure proper functionality.
Software is then used to “place” the high level design onto a digital device by implementing the various functions of the design in various CLBs or other logic elements or groups of elements. The design may again be tested after the design has been placed on the device. At that point, the functionality of the design and the behavior of the device are simulated and tested to ensure, for example, that timing constraints are met. Often at this stage engineers need to correct timing issues by changing the manner in which the design was placed on the device. This often involves the use of special software to reconfigure or reconnect CLBs.
Once simulated testing has been completed, a device is configured according to the design. Such devices are typically configured by a configuration bitstream generated by the design software, wherein each bit or subcombination of bits in the bitstream indicates, for example, which CLBs are used and how the CLBs are configured and interconnected. The configuration bitstream is communicated to the device via an input port of the device and is stored, for example, in static memory cells wherein the values in the cells control all programmable elements on the device, including routing resources.
Developments in technology have increased the functionality of programmable logic devices. Advancing technology, for example, enables manufacturers to create devices with smaller, faster and more densely placed logic elements. Such devices are more robust than their predecessors. As demand for a new generation of programmable devices increases, demand for the previous-generation of devices declines accordingly and manufacturers eventually discontinue production of the older devices.
In addition, as the new generation of devices become available, it would reduce costs if the old design could be used in the new device. Unfortunately, replacing the previous device is not as simple as placing the new device in the product and configuring it with the previous configuration bitstream.
Re-implementing a design in a new programmable logic device can consume a great deal of time and money, particularly if the design is complex. Because the new device is built differently and includes new functionality, the configuration bitstream used in the previous device cannot be used “as is” to configure the new device. A common way of migrating an existing design to a new device is to begin with the high level design (VHDL, Verilog, schematic, etc.) and compile the design specifically for the new device. This is a time-consuming process because the design has to be resimulated and retested to ensure timing constraints are met. Furthermore, if the design does not conform to the timing or other requirements of the design, engineers have to spend additional time adjusting the layout of the design on the new device, or possibly even redesign a portion of the design, to make the new device compatible with the product.
These challenges can be further complicated if a user desires to replace the original device with a new device made by a different manufacturer. The user may discover, for example, that a device developed by another manufacturer would be the best fit or most cost effective replacement. Fundamental differences in architecture between the original device and the new device may require extensive redesign far in excess of what would be required if the design were implemented in a successive-generation device.
One method of avoiding the time-consuming migration process described above involves designing successive generations of programmable devices to be operable to interpret configuration bitstreams from previous generation devices. While this eliminates the need to go through a lengthy redesign process, it suffers from various limitations. Each device, for example, would require extra logic elements operable to determine to which generation an incoming bitstream pertains and to modify the bitstream accordingly to fit the newer device. It will be appreciated that these logic elements would need to be placed on each programmable device, adding to the overall cost of each device. Furthermore, with such a solution it would be difficult or impossible take advantage of new functionality, such as firm cores, in the newer device to improve design performance. Furthermore, such backwards compatible hardware may not be compatible with designs implemented on other families of devices, and almost certainly would not be compatible with designs implemented on devices made by other manufacturers.
Due to the above-mentioned and other problems and disadvantages in the art, a need exists for a method of converting a design implemented on an earlier-generation PLD to a design compatible with a successive generation PLD, wherein the conversion does not require extensive redesign or testing of the new PLD and does not require dedicated logic elements on the new PLD.